The present invention relates to silicide blocking processes during integrated circuit (IC) fabrication. More particularly, the present invention relates to forming metal silicides on certain areas of integrated circuits (ICs) and effectively blocking metal silicide formation on other areas of ICs.
Metal silicide or "silicide", as it is commonly known in the (integrated circuit) IC art, is typically formed at contact areas of MOS (metal oxide semiconductor) device elements, e.g., gate electrode, source and drain regions, by fusing together metal ions from a metal layer and silicon ions from the device elements. As used herein the term "contact area," refers to a top portion of the device element from where connections to other devices elements or IC features is made. The presence of silicide at a contact area increases the conductivity of the contact area and thereby facilitates a solid electrical connection between device elements and metal contacts. Commonly formed silicides include titanium disilicide (TiSi.sub.2) and cobalt disilicide (CoSi.sub.2). It is desirable to form silicide at contact areas of devices elements in logic and SRAM (Static Random Access Memory) areas of the IC because silicide formation in such areas dramatically reduces the RC gate delay and improves resistance of devices in series.
It is, however, undesirable to form silicide above the device elements in IC areas that are dedicated to implementing DRAM (Dynamic Random Access Memory), input/output and analog applications. By way of example, on the source and drain regions of a DRAM transistor device, silicide formation increases the p-n or n-p junction leakage and degrades the memory refresh time. As another example, in the input/output pad circuitry, the presence of silicide degrades the electrostatic discharge protection. As yet another example, in the analog area of the IC, where resistors are frequently employed, silicide formation lowers the resistance of the resistors.
FIG. 1 shows an idealized IC surface 10 having arranged thereon an input/output pad area 12 near the periphery of IC 10, a logic area 14 containing a plurality of devices dedicated to performing logic applications of the IC adjacent to input/output pad area 12, an analog area 16 positioned below logic area 14 and a DRAM (dynamic random access memory) area 18 positioned adjacent to logic area 12. For the above mentioned reasons, the formation of silicide on the device elements in DRAM area 18, input/output pad area 12, and analog area 16 should be prevented or such areas must undergo silicide blocking when silicide is being formed above device elements in logic area 14, for example.
One current approach, sometimes referred to as "ultrasonic vibration technique," of silicide blocking on a portion of a partially fabricated IC is set forth in FIGS. 2A-2D. FIG. 2A shows a partially fabricated IC surface including MOS (Metal Oxide Semiconductor) transistor devices 22 and 24, which are fabricated according to conventional methods well known to those skilled in the art. Device 24 may be located in DRAM area 18, input/output pad area 12 or analog area 16 of FIG. 1, for example, and therefore undergoes silicide blocking, i.e. the contact areas of the elements of device 24 are blocked or prevented from undergoing silicide formation. Devices 24 and 22 are separated by a field oxide 36 and device 22 may be located in logic area 14 of FIG. 1, for example.
Device 22 of FIG. 2A includes a channel region 52 separating a heavily doped source region 32 with an associated lightly doped "tab" 32A and a heavily doped drain region 34 with an associated lightly doped "tab" 34A. An insulating gate oxide 30 is formed between the surface of device 22 and a gate electrode 26, which is flanked by silicon dioxide (hereinafter referred to as "oxide") spacers 28A and 28B on both sides. Device 24 similarly includes a channel region 54, a heavily doped source region 44 with an associated lightly doped "tab" 44A, a heavily doped drain region 46 with an associated lightly doped "tab" 46A, an insulating gate oxide 42, a gate electrode 38 and oxide spacers 40A and 40B in substantially the same configuration as device 22.
A photoresist layer is blanket deposited on the IC surface and then patterned by conventional photolithography to mask those portions of the IC that require silicide blocking. FIG. 2A shows a photoresist layer 48 masking the surface of device 24 and exposing device 22. A metal layer 50, e.g., cobalt or titanium, is then blanket deposited over the IC surface of FIG. 2A, as shown in FIG. 2B. Next, the partially fabricated IC of FIG. 2C is formed when a portion of metal layer 50 along with photoresist layer 48 disposed atop device 24 is removed or lifted-off by subjecting the IC surface to ultrasonic vibrations. A portion of metal layer 50 deposited above device 22, however, remains on the IC surface as shown in FIG. 2C.
A thermal reaction between metal ions of layer 50 above device 22 and silicon ions at polysilicon gate electrode 26 at a temperature of between about 400 and about 700.degree. C. fuses together the metal and silicon ions to form a first silicide contact area 56 on gate electrode 26, as shown in FIG. 2D. Metal ions of layer 50 similarly fuse with the silicon ions at source 32 and drain 34 to form a second and third silicide contact area 58 and 60, respectively. The temperature range mentioned above, however, is not high enough for the metal ions in metal layer 50 to react with the oxide spacers disposed below. Portions of metal layer deposited above spacers 28A and 28B are removed, as shown by FIG. 2D, by a wet etch solution. By way of example, for titanium metal layer etching, the wet etch solution contains water (H.sub.2 O), ammonia (NH.sub.4 OH) and hydrogen peroxide (H.sub.2 O.sub.2) at a ratio of 4:1:1, respectively and for cobalt metal layer etching, the wet solution contains water (H.sub.2 O) sulfuric acid (H.sub.2 SO.sub.4) and hydrogen peroxide (H.sub.2 O.sub.2) at a ratio of 4:3:1, respectively.
Unfortunately, as the current IC technology strives to significantly reduce IC feature sizes, it is difficult to completely lift-off the metal layer by ultrasonic vibrations from above a certain device, such as device 24 of FIG. 2C, because such a technique is relatively imprecise. As a result, some metal may remain and undesirably form silicide above the device elements of the DRAM, input/output pads and analog areas of the IC, for example. Furthermore, after a substantial portion of the photoresist layer is removed, the photoresist residue contaminates the areas above the device elements on the IC surface where silicide contact areas are subsequently formed. The contaminated metal-silicon interface forms a contact area that provides a weak electrical connection to other device elements and features of the IC.
A second approach (hereinafter referred to as the "LTO deposition technique") currently employed for silicide blocking is set forth in FIGS. 3A-3F. As shown in FIG. 3A, a low temperature oxide (LTO) 62is blanket deposited on the surface of the partially fabricated IC of FIG. 2A. A photoresist layer 64 is then patterned by conventional photolithography to mask those regions of the IC surface that require silicide blocking. FIG. 3B shows that a photoresist layer 64 masks device 24, but not device 22. LTO layer 62 above the unmasked device 22 is then etched using hydrofluoric acid (HF) to form the partially fabricated structure shown in FIG. 3C. Next, the structure shown in FIG. 3D is formed when photoresist layer 64 above device 24 is removed by techniques, e.g., wet etching and ashing, well known to those skilled in the art. A metal layer 66 is blanket deposited on the surface of the partially fabricated IC, as shown in FIG. 3E.
The partially fabricated IC surface then undergoes heat treatment at a temperature of between about 400 and about 700.degree. C. and the metal ions of layer 66 above device 22 fuse with the silicon ions at polysilicon gate electrode 26 to form a first silicide contact area 56 on gate electrode 26, as shown in FIG. 3F. Similarly, metal ions of layer 66 fuse with the silicon ions at source 32 and drain 34 to form a second and third silicide contact areas 58 and 60, respectively. It should be borne in mind that this temperature range is not high enough for LTO layer 62 to react with metal layer 66 above device 24. Next, unreacted metal layer 66 overlying contact areas 56, 58 and 60, spacers 28A and 28B and device 24 is removed by well known etching techniques mentioned above to form the structure shown in FIG. 2D. LTO layer 62 on device 24 of FIG. 3F may not be removed and may be incorporated into interlayer dielectric (ILD) formed above the gate electrode.
Unfortunately the LTO deposition technique suffers from several drawbacks. By way of example, the LTO deposition technique requires extra steps of depositing, patterning and etching an LTO layer. This translates into a lower throughput for the IC fabrication process. As another example, removal of LTO layer 62 above device 22 in FIG. 3C by etching using HF may at least partially dissolve oxide spacers 28A and 28B. As a result, the oxide spacers are severely damaged and there is poor isolation between the gate electrode and source and drain.
Additionally, in the two approaches described above, as well as in all the conventional silicide blocking methods, contact areas formed at a top portion of the device elements are often thin and rough due to the conventional step of reactive ion etching (RIE) of the oxide layer to form spacers. These damaged areas create a poor reactive site between metal and silicon ions to form silicide thereon.
What is therefore needed is an effective silicide blocking process to block or prevent silicide formation above preselected device elements.